JEDEC JESD51-3

Description

JEDEC JESD51-3 – LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES

This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements, minimum trace lenghts, trace thickness, and routing considerations. Application includes still air and moving air thermal tests.

Product Details

Published:

08/01/1996

Number of Pages:

11

File Size:

1 file , 330 KB

Note:

This product is unavailable in Russia, Ukraine, Belarus